The present invention relates to a sense amplifier and, more particularly, to a current-mirror type sense amplifier.
A differential amplifier type CMOS (Complementary Metal Oxide Semiconductor) sense amplifier using a current-mirror circuit as a load has been used in a conventional CMOS static RAM (Random Access Memory) or a conventional nonvolatile ROM (Read Only Memory) to detect data. Typical conventional sense amplifiers are exemplified in FIGS. 1 to 3.
In the conventional circuit of FIG. 1, transistors Q1 and Q2 are N channel MOS transistors constituting a differential amplifier, and transistors Q3 and Q4 are P channel MOS transistors constituting a current-mirror circuit as a load. Complementary differential input signals IN and IN are input to the gates of transistors Q1 and Q2, respectively. Complementary output signals OUT and OUT appear at junction N1 between transistors Q1 and Q3, and at junction N2 between transistors Q2 and Q4, respectively.
In the sense amplifier of FIG. 1, when input signals IN and IN are input through input signal lines 1 and 2, complementary output signals OUT and OUT amplified by the differential amplifier appear on output signal lines 3 and 4. If the voltage of input signal IN is lower than that of input signal IN, output signal OUT becomes high potential VOH and output signal OUT becomes low potential VOL. As the gate and drain of transistor Q3 are interconnected, high potential VOH is increased to only (VDD-.vertline.VTHP.vertline.), where VTHP is the threshold voltage of transistor Q3. Low potential VOL is determined by a ratio of the conductance of transistor Q4 to that of transistor Q2. Because of this, potential difference (VOH-VOL) does not exceed (VDD-.vertline.VTHP.vertline.-VOL). Therefore, the output amplitude of the sense amplifier becomes relatively low and the operation margin of the resultant memory is small.
In the conventional circuit of FIG. 2, transistors Q5 and Q6 are inserted between transistors Q3 and Q1 and between transistors Q4 and Q2, respectively. An enable signal (SAE) is supplied to the gates of transistors Q5 and Q6 to enable sensing of the sense amplifier. In the conventional circuit of FIG. 3, N channel switching transistor Q7 is inserted between transistors Q1 and Q2 and low power source potential VSS. An enable signal (SAE) is supplied to the gate of transistor Q7 to enable sensing of the sense amplifier.
In the circuits of FIGS. 2 and 3, the gate and drain of transistor Q3 are interconnected in the same manner as in FIG. 1, and high potential VOH is increased to only (VDD-.vertline.VTHP.vertline.). Therefore, output voltage (VOH-VOL) also does not exceed (VDD-.vertline.VTHP.vertline.-VOL). In the same manner as in the conventional arrangement of FIG. 1, the output amplitude of the sense amplifier is low, and the memory operation margins for variations in power source potential and characteristics of the transistors are inevitably small.